(a) Field of the Invention
The present invention relates to plasma display panels (PDPs), and, more particularly, to a driving method therefor.
(b) Description of the Related Art
A PDP is a flat display for showing characters or images using plasma generated by gas discharge. PDPs can include pixels numbering more than several million in a matrix format, in which the number of pixels are determined by the size of the PDP. Referring to FIGS. 1 and 2, a PDP structure will now be described.
FIG. 1 shows a partial perspective view of the PDP, and FIG. 2 schematically shows an electrode arrangement of the PDP.
As shown in FIG. 1, the PDP includes glass substrates 1, 6 facing each other with a predetermined gap therebetween. Scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on glass substrate 1. Scan electrodes 4 and sustain electrodes are covered with dielectric layer 2 and protection film 3. A plurality of address electrodes 8 is formed on glass substrate 6, and address electrodes 8 are covered with insulator layer 7. Barrier ribs 9 are formed on insulator layer 7 between address electrodes 8, and phosphors 10 are formed on the surface of insulator layer 7 and between barrier ribs 9. Glass substrates 1, 6 are provided facing each other with discharge spaces between glass substrates 1, 6 so that scan electrodes 4 and sustain electrodes 5 can cross address electrodes 8. Discharge space 11 between address electrode 8 and a crossing part of a pair of scan electrodes 4 and sustain electrodes 5 forms discharge cell 12, which is schematically indicated.
As shown in FIG. 2, the electrodes of the PDP have an n×m matrix format. Address electrodes A1 to Am are arranged in a column direction, and n scan electrodes Y1 to Yn and n sustain electrodes X1 to Xn are arranged in a row direction. Scan/sustain driving circuit 13 drives the scan and sustain electrodes, while address driving circuit 15 drives the address electrodes.
U.S. Pat. No. 6,294,875 by Kurata for driving a PDP discloses a method for dividing one field into eight subfields and applying different waveforms in the reset period of the first subfield and the second to eighth subfields.
As shown in FIG. 3, a subfield includes a reset period, an address period, and a sustain period. A ramp waveform which gradually rises from voltage Vp of less than a discharge firing voltage to voltage Vr that is greater than the discharge firing voltage is applied to scan electrodes Y1 to Yn during the reset period of the first subfield. Weak discharges are generated to address electrodes A1 to Am and sustain electrodes X1 to Xn from scan electrodes Y1 to Yn while the ramp waveform rises. Negative wall charges are accumulated to scan electrodes Y1 to Yn, and positive wall charges are accumulated to address electrodes A1 to Am and sustain electrodes X1 to Xn because of the discharges. The wall charges are actually formed on protection film 3 on scan electrodes 4 and sustain electrodes 5 in FIG. 1, but the wall charges are described as being generated on scan electrodes 4 and sustain electrodes 5 below for ease of description.
A ramp voltage which gradually falls from voltage Vq of less than the discharge firing voltage to voltage 0V (volts) is applied to scan electrodes Y1 to Yn. A weak discharge is generated on scan electrodes Y1 to Yn from sustain electrodes X1 to Xn and address electrodes A1 to Am by a wall voltage formed at the discharge cells while the ramp voltage falls. Part of the wall charges formed on sustain electrodes X1 to Xn, scan electrodes Y1 to Yn, and address electrodes A1 to Am are erased by the discharge, and they are established to be appropriate for addressing. In a like manner, the wall charges are actually formed on the surface of insulator layer 7 of address electrode 8 in FIG. 1, but they are described as being formed on address electrode 8 for ease of description.
Next, when positive voltage Vw is applied to address electrodes A1 to Am of the discharge cells to be selected, and 0V is applied to scan electrodes Y1 to Yn in the address period, addressing is generated between address electrodes A1 to Am and scan electrodes Y1 to Yn, and between sustain electrodes X1 to Xn and scan electrodes Y1 to Yn by the wall voltage caused by the wall charges formed during the reset period and positive voltage Vw. By the addressing, positive wall charges are accumulated on scan electrodes Y1 to Yn, and negative wall charges are accumulated on sustain electrodes X1 to Xn and address electrodes A1 to Am. Sustaining is generated on the discharge cells on which the wall charges are accumulated by the addressing, by a sustain pulse applied during the sustain period.
A voltage level of the last sustain pulse applied to scan electrodes Y1 to Yn during the sustain period of the first subfield corresponds to voltage Vr of the reset period, and voltage (Vr-Vs) corresponding to a difference between voltage Vr and sustain voltage Vs is applied to sustain electrodes X1 to Xn. A discharge is generated from scan electrodes Y1 to Yn to address electrodes A1 to Am because of the wall voltage formed by the addressing, and sustaining is generated from scan electrodes Y1 to Yn to sustain electrodes X1 to Xn in the discharge cells selected in the address period. The discharges correspond to the discharges generated by the rising ramp voltage in the reset period of the first subfield. No discharge occurs in the discharge cells which are not selected since no addressing is provided in the discharge cells.
In the reset period of the second following subfield, voltage Vh is applied to sustain electrodes X1 to Xn, and a ramp voltage which gradually falls from voltage Vq to 0V is applied to scan electrodes Y1 to Yn. That is, the voltage which corresponds to the falling ramp voltage applied during the reset period of the first subfield is applied to scan electrodes Y1 to Yn. A weak discharge is generated on the discharge cells selected in the first subfield, and no discharge is generated on the discharge cells that are not selected.
In the reset period of the last following subfield, the same waveform as that of the reset period of the second subfield is applied. An erase period is formed after the sustain period in the eighth subfield. A ramp voltage which gradually rises from 0V to voltage Ve is applied to sustain electrodes X1 to Xn during the erase period. The wall charges formed in the discharge cells are erased by the ramp voltage.
As to the above-described conventional driving waveforms, discharges are generated on all the discharge cells by the rising ramp voltage in the reset period of the first subfield, and accordingly, the discharges problematically occur in the cells which are not to be displayed, thereby worsening the contrast ratio. Further, since the addressing is sequentially performed on all scan electrodes in the address period of using an internal wall voltage, the internal wall voltage of scan electrodes that are selected in the later stage is lost. The lost wall voltage reduces margins as a result.